EEPROMs have been commercially available from the early 1980's and have become increasingly incorporated in applications requiring reliable nonvolatile memory that can be altered while incorporated in working circuitry. EEPROM devices, however, generally required cell sizes three to four times as large as more conventional erasable programmable read-only memories (EPROMs) or dynamic random access memory (DRAM) manufactured by the same scale technology. Thus, EEPROMs also had a significantly lower density and a corresponding higher cost than EPROMs or DRAMs.
Efforts to improve the density of EEPROM devices while reducing their associated cost by limiting features incorporated in the devices led to the development of so called Flash EEPROM devices. In particular, the Intel Corporation of Folsom, California developed a Flash EEPROM technology referred to as ETOX in which a memory cell is programmed when high voltages are applied to both a drain and control gate of the memory cell while source of the cell grounded. Under these conditions, a current flows from the drain to the source which creates hot electrons in the vicinity of a drain pinch-off region of the cell. Some of the hot electrons are collected by a floating gate of the cell which is coupled to a high potential by the voltage applied to the control gate. The memory cell is erased by applying a high positive voltage to the source with the control gate held at ground. A high electric field appears across a thin oxide layer between the floating gate and the source which causes electrons to quantum mechanically tunnel from the floating gate to the source which erases the cell. When implemented in an array, the sources of the memory cells in the array are connected in common so that the entire array can be simultaneously "Flash" or bulk erased.
While the ETOX cell technology offers many advantages over conventional EEPROM technologies in a variety of applications, there are many applications in which small blocks or sectors of data need to be altered in the memory while the remaining data is retained. In such cases, the bulk erase feature of the above-described memory device becomes a liability. It becomes necessary to provide a secondary memory media or storage buffer where the contents of the memory device are stored before performing the bulk erase operation. The altered sector may then be written to the memory device and the unaltered sectors retrieved from the secondary memory media. The disadvantages from using a secondary memory media are obvious, namely, more memory space is required by the system as a whole and the time required to alter a sector of data is greatly increased.
Flash EEPROM architectures have been proposed that would overcome the disadvantages of the bulk erase feature discussed above by permitting individual bytes of data to be erased. U.S. Pat. No. 4,949,309 issued to Rao, for example, discloses an array of floating gate transistors connected so that some of the floating gate transistors within the array can be erased without affecting the state of other floating gate transistors within the array. Alternatively, the entire array of floating gate transistors can be simultaneously erased. The byte erase feature is accomplished by dividing the sources of the memory cells into groups that are commonly connected to bulk erase transistors. Each bulk erase transistor can be individually addressed to selectively permit the erasing of the memory cells coupled thereto.
There are a number of disadvantages, however, to the architecture employed to provide the byte erase feature. For example, a significant area penalty results from the addition of the bulk erase transistors and the associated address lines required to control the operation of the bulk erase transistors which increases die cost and reduces potential yield, as well as lowering the potential density of the memory device. In addition, the bulk erase transistor also acts as an additional impedance on the source during programming which may cause difficulties during programming operations.
In view of the above, it would be desirable to provide a Flash EEPROM architecture having a sector erase capability that did not have the associated area penalty of conventional byte erasable Flash EEPROM devices. It would further be desirable to provide a Flash EEPROM architecture having a sector erase capability that by making a simple structural modification of conventional Flash EEPROM architectures, thereby reducing the time and expense associated with the development of a new memory architecture.